1. Field of the Invention
The present invention relates to a plasma display panel (PDP) and a method for driving the same, and more particularly, to a PDP that may be normally driven even when an abnormal vertical synchronous signal is input thereto.
2. Discussion of the Related Art
PDPs have been recently highlighted among flat panel displays due to their high luminance, high luminous efficiency and wide viewing angle.
The PDP uses plasma generated by gas discharge to display characters or images. The PDP may include several tens of thousands to millions of pixels arranged in a matrix format.
Generally, the PDP includes a pair of spaced glass substrates on which electrodes are formed and fluorescent materials are coated, and plasma formed in the space between the substrates.
FIG. 1 is a plan view of a conventional PDP.
As shown in FIG. 1, the PDP comprises sustain electrodes 2 and scan electrodes 6 arranged in parallel in pairs, where each pair constitutes one display line.
Address electrodes 4 are arranged orthogonally to the sustain electrodes 2 and scan electrodes 6. Discharge cells (first to last discharge cells) are formed at intersections between the address electrodes 4, which are arranged in a column direction, and the pairs of sustain electrodes 2 and scan electrodes 6, which are alternately arranged in a row direction.
Address display separating (ADS) driving is widely used as a method for driving the PDP in which the discharge cells are formed as described above.
Basically, the ADS driving method includes a reset period, an address period and a sustain period.
In detail, one frame is divided into a plurality of sub-fields, and each subfield is further divided into the reset period, the address period and the sustain period. These sub-fields are basic units of a frame, and 8 to 12 sub-fields are typically used to form one frame to express one image.
In the reset period, the state of each cell is initialized to facilitate an addressing operation on the cell.
In the address period, cells that are to display an image are selected. At this time, wall charges are formed in the selected cells due to an address discharge.
In the sustain period, a discharge occurs to display an image on the addressed (selected) cells.
Eight to 12 sub-fields per frame may be used to display a desired image (luminance) by adjusting the number of sustain pulses. The 8 to 12 sub-fields have different weights, and they are sequentially operated.
The frequency of a vertical synchronous signal (“Vsync”) is a very important factor in expressing a gray scale using a plurality of sub-fields having different weights. FIG. 2 shows a waveform of the scan electrode 6 when the Vsync is generated.
Specifically, FIG. 2 shows a waveform diagram of the scan electrode 6 in the first sub-field after inputting Vsync.
As shown in FIG. 2, when the Vsync is input, the scan electrode 6 goes through a Ground period a, a pre-sustain period b and a ramp reset period c. A pre-sustain waveform is output in the pre-sustain period b, and a ramp erase pulse is output in the ramp reset period c. However, when the Vsync is input when one sub-field is not finished, as in an operation such as a channel search function, the first sub-field of the scan electrode 6 is restarted in the middle of the sub-field. It is not finished. Consequently, in the worst case where the Vsync starts at a ramp peak of an output waveform of the scan electrode 6 as shown in FIG. 3, excessive displacement current may flow in the panel, which may damage switches that are not able to withstand a high current.
A video signal typically has a Vsync frequency period of 16.67 ms for National Television System Committee (NTSC) and 20 ms for Phase Alternate Line (PAL).
A PDP driving control circuit is adapted to receive a Vsync of such a video signal and generate a control signal for a driving circuit by using the received Vsync as a reference signal.
Accordingly, when a Vsync having a normal period is input, the PDP driving control circuit performs normally. However, when a Vsync with an abnormal period is input, the PDP driving control circuit may perform abnormally.
A Vsync with an abnormal period may often be generated in a transient state such as changing a channel. When an abnormal Vsync is input, a failure mode may occur as follows.
For example, where the driving state is a reset state, the PDP driving control circuit is initialized once the Vsync with an abnormal period is input. In this case, a control signal disappears when a field effect transistor (FET) of the driving circuit is turned on, thereby causing the driving circuit to enter an abnormal state. As a result, the driving FET may be damaged due to a displacement current.